Cerebras Systems

Contribution to AI

The unexamined constraint in chipmaking was that a processor must fit inside a single lithographic reticle, roughly 800 square millimetres, and that anything larger had to be built by wiring separate dies together. Wafer-scale integration had been tried commercially once, by Gene Amdahl's Trilogy Systems in the 1980s, and its collapse was thorough enough to settle the question for thirty years. The 2019 Wafer-Scale Engine reopened it: 46,225 square millimetres of silicon holding 1.2 trillion transistors, 400,000 cores and 18 gigabytes of on-chip memory, with defects handled by making each core tiny and routing traffic around the dead ones rather than by hoping for a flawless wafer. What that bought was architectural rather than merely large. Weights sat in SRAM one clock cycle from the arithmetic, so the off-chip memory trip that dominates transformer inference simply did not occur, and the work of splitting a model across thousands of devices moved from the programmer's problem to the hardware's. By the third generation in 2024 the count stood at four trillion transistors and 900,000 cores. The commercial demonstration came with inference speeds — hundreds and then thousands of tokens per second on Llama models — which established that the latency floor everyone had accepted was a property of GPU memory hierarchies, not of the models themselves. National laboratories bought the systems; the monoculture acquired a credible alternative.

Drafted with AI and edited by hand (claude-opus-5, reviewed 2026-08).