Graphcore

Contribution to AI

A GPU multiplies large dense matrices at speed and fetches its operands from attached memory; the wager made in Bristol was that neither property was essential to machine learning. The Colossus IPU took the opposite position on both counts — the first-generation GC2, powered on in 2018 on TSMC's 16nm process, carried 1,216 independent processor tiles, each running its own programs against its own slice of SRAM, with roughly 300 megabytes of memory held on the chip itself rather than in external DRAM ; the 2020 GC200 raised that to 1,472 tiles and 900 megabytes . Coordination came from bulk synchronous parallel execution, alternating compute and exchange phases under a compiler's schedule rather than caches and coherence hardware, which made the Poplar graph compiler as much a part of the architecture as the silicon. The result was the field's most fully realised fine-grained MIMD alternative to the GPU's SIMT model, and it was tested where others could see it: IPUs reached Microsoft Azure as the NDv3 preview in 2019 , and MLPerf entries from 2021 replaced vendor claims with audited times to train. The Bow generation of 2022 was the first processor shipped using TSMC's wafer-on-wafer 3D bonding, stacking a power-delivery die beneath the compute die . The 2024 sale to SoftBank for less than the company had raised stands as the field's plainest evidence that a better architecture loses to a familiar software stack.

Drafted with AI and edited by hand (claude-opus-5, reviewed 2026-08).